Renesas Electronics /R7FA6M3AH /EPTPC0 /TSLATR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TSLATR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0EGP0INGP

Description

Timestamp Latency Setting Register

Fields

EGP

Input Port Timestamp Latency SettingThese bits hold the setting for the time stamp latency (ns) for the input ports.

INGP

Output Port Timestamp Latency SettingThese bits hold the setting for the time stamp latency (ns) for the output ports.

Links

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